1. Field of the Invention
The present invention relates to the field of data storage. More particularly, the present invention relates to a magneto-resistive memory cell for a cross point memory array and a technique for biasing the magneto-resistive memory cell.
2. Description of the Related Art
FIG. 1 depicts a magneto-resistive (MR) element memory array that is organized as a cross point array. Individual memory cells are formed at the crossing points of bits lines (BL) and word lines (WL). An array of magnetic memory cells is often called a magnetic random access memory (MRAM). For cross point arrays using MR memory cells based on an anisotropic magnetoresistive (AMR) effect for storing information, cell resistive values are on the order of 10 to 100 Ohms. For the cross point array of FIG. 1, the MR cells use magnetic tunnel junctions (MTJ) that can have a resistive cell value that is on the order of 1000 to 100,000 Ohms, and having a magnetoresistive effect of 10% to 30%. Consequently, a cross point array using MTJ memory cells has a significantly lower power dissipation level than that of an array using AMR memory cells.
Nevertheless, cross point arrays having memory cells using only MR elements are not practical unless each cell includes a selection device because there are many sneak paths from a selected bit line through unselected word lines, then through unselected bit lines, and finally to the selected word line. To make a cross point array practical, a selection device, such as a diode having a current-voltage characteristic like that shown in FIG. 2, can be included in each memory cell for preventing sneak path conduction. Use of such a selection device also further reduces power dissipation of the array because the current used for sensing a cell flows only through a single magnetic tunnel junction.
FIG. 1 shows a cross point array 10 having memory cells 11 formed from a magnetic tunnel junction device MTJ and a diode D. Such a cross point array is described in U.S. Pat. No. 5,640,343 to W. G. Gallagher et al. and incorporated by reference herein. The biasing range for the diode selection device used in the Gallagher et al. memory cell is from about 1 V forward voltage to about 1 V reverse voltage. During a write operation, or between read and write operations, all word lines are held at their unselected bias levels Vw, which is about 1 V greater than the bias level Vb of the unselected bit lines. Thus, all selection device diodes remain reversed-biased during a write operation, or between read and write operations, as represented by point U in FIG. 2.
For cross point array 10 of FIG. 1, a cell S is read or sensed by a bit line BL1 being selected and brought to bias level Vw, and a word line WL1 being selected and brought to bias level Vb, so that only the diode of selected cell S is forward-biased. To write a zero or a one to a cell, bit line currents in opposite directions are used and, in order to generate these currents, a ground potential is avoided for the unselected bit line voltage Vb, which is typically about 1 V. Therefore, the arrays have unselected word lines that are at a voltage Vw, that is, at about 2 V. The sensing circuitry connected to the selected bit line has, as expected in known circuit design practice, a third bias level that is significantly higher than 2V. The power supply for the circuitry controlling such an array must be capable of supplying three bias potentials, with one of the bias potentials being greater than is desirable for deep sub-micron VLSI technology. Also, for the cross point array of FIG. 1, a bit line bias voltage must change by 1 V to read a selected cell, requiring substantial time to complete a read operation.
Even though the current through a conventional diode selection device goes to zero for a zero bias voltage, the resistance of the diode approaches a relatively low non-zero value in the sense that the resistances of cells connected to a selected bit line can still have an effect on the sensing of the resistance value of cell S because of slight variations in voltage on the bit line at sense time. Thus, a high zero-bias resistance is desired for the selection device.
FIG. 3 shows a current-voltage characteristic for a bidirectionally conducting nonlinear resistance element. If such a resistance element is used as a memory cell selection device in the cross point array of FIG. 1, a substantial sneak-path current would flow from unselected word lines that are biased at Vw (about 2 V) through cells to unselected bit lines that are biased at Vb (about 1 V). This undesirable condition is represented by point X in FIG. 3. Consequently, for the cross point array of FIG. 1 to have a useful number of memory cells using a bidirectionally conducting nonlinear resistance element for a selection device, the power dissipated by the sneak-path current would significantly exceed the power dissipated when sensing a selected cell S.
Additionally, portions of unselected word lines would have a potential that is below Vw because of a voltage drop caused by sneak-path currents passing through unavoidable series resistances existing in practical VLSI circuit lines. Thus, the diodes in unselected cells connected to the selected bit line indicated by an "F" in FIG. 1 would be forward biased. Sneak currents, as represented by point F' in FIG. 3, would flow through many F-type cells for each selected cell S, interfering with the sensing of cell S.
Consequently, bidirectionally conducting nonlinear resistance selection devices having a symmetrical current-voltage characteristic, like the current-voltage characteristic shown in FIG. 3, or devices having a lower turn-on voltage for conduction in the reverse bias direction than in the forward bias direction, like the current-voltage characteristic for a backward diode shown in FIG. 4, would naturally be avoided for magneto-resistive memory arrays.
What is needed is a nonvolatile cross point memory array having memory cells that are capable of operating at voltages and power levels that are suitable for integration using deep sub-micron VLSI technologies. What is also needed is a memory cell having a cell selection device providing a low series resistance and a low voltage biasing, thereby providing a low power cross point memory array than conventional cross point memory arrays. Further, what is needed is an MR memory cell having operating biasing points providing a reduced voltage swing required for selecting a bit line so that sensing times are thereby shorter than conventional MR memory cells. Further still, what is needed is a cross point memory array that uses a bias level that minimizes power dissipation in the array.